Digital Design Engineer for Accelerator ASIC

Cambridge, MA · Job # 8077BK

Our client company is seeking a digital design engineer for developing FPGA / ASIC with the purpose of integrating high-bandwidth, low-latency nanophotonic processor into computer systems.

Responsibilities:

  • Understand the overall application of the chip, proposing and developing improvements in overall design.
  • Design and document one or more blocks of an ASIC, including functionality and timing.
  • Implement designs in RTL (System Verilog or other HDLs).
  • Create simple test benches and debug complex logic simulations.
  • Work closely with software teams on functionality, interfaces, and documentation.
  • Managing data stream into and out of the ONN accelerator.

Preferred Qualifications:

  • MS degree in EE or higher, preferably with 3 years or more of experience.
  • 4 years of experience in FPGA/ASIC design and experience with ASIC development.
  • Expert in communication protocols  (e.g. PCI, PCIe, Fibre Channel, Ethernet, SCSI, I2C, AXI, DDR)
  • Experience with highly pipelined designs, and with multiple-clock-domain designs.
  • Experience with computer arithmetic.
  • Experience with performance modeling.
  • Knowledge of processor design, accelerators, and/or memory hierarchies. Knowledge of machine learning algorithms.
  • Programming languages: HDL coding, FPGA tools, Simulation tools, Timing analysis.
  • Familiarity with advanced verification techniques such as coverage driven testing, assertions, and formal verification.
  • Operating general lab equipment (DMM, oscilloscope, logic & bus analyzers, device programmers)
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